Anritsu demonstrated receiver testing using Synopsys DesignWare IP for PCI Express 5.0 at PCI-SIG Developers Conference 2019

Anritsu demonstrated leading-edge PCI Express (PCIe) 5.0 technology using the Anritsu Signal Quality Analyzer-R MP1900A high-performance Bit Error Rate Tester (BERT) and Synopsys DesignWare IP for PCI Express 5.0 during the PCI-SIG Developers Conference 2019, held June 18-19 in Santa Clara, CA. The demonstration showed how to generate stressed signals using the MP1900A and 5.0 compliance board and how to evaluate the receiver stressed input characteristics using 5.0 patterns.

The recently released PCIe 5.0 specification with speeds of 32 GT/s requires new measuring instruments supporting 5.0 patterns and crosstalk tests. Anritsu’s MP1900A solution with high-quality signals for PCIe 5.0 test patterns and multi-channel expandability for crosstalk tests can be expanded easily from PCIe 4.0 at 16GT/s to PCIe 5.0 at 32GT/s.

Leading the market in early PCIe 5.0 testing, the MP1900A BERT supports high-speed computer bus interfaces, such as PCI Express 5.0 and USB 3.2, as well as next-generation 400G Ethernet communications interfaces. Synopsys DesignWare IP for PCIe consist of silicon-proven controllers, PHYs, and verification IP, which are designed to support all required features of PCIe 5.0, 4.0, 3.1, 2.1, 1.1, and PIPE specifications.

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